UMC Sync Cache Modil 256KB (Pipeline pete kachèt, KÒT)
Afiche pa DeviceLog.com | Afiche nan SRAM | Afiche sou 2013-01-05
2
Anpil mainboards, sipòte byen bonè Pentium CPU, anjeneral te gen senkronize kachèt memwa chips kòm CPU L2 kachèt. Modil kachèt senkronize sa a(KÒT; Cache Sou Yon Baton) se modil memwa ekstèn yo itilize kòm kachèt CPU L2 adisyonèl. Li maksimize pèfòmans nan processeur a pandan y ap processeur a ap tann pou enstriksyon oswa done. L2 cache is used for operating closer to the theoretical limit of the microprocessor.
‘Pipelining’ suggests that the transfers after the first transfer happen before the first transfer has arrived at the processor. ‘Pipleline burst cache’ was developed as an alternative to asynchronous cache and synchronous burst cache.
- Non pwodwi : UMC Sync Cache Modil 256KB (Version : 1.8)
- Nimewo Pati : LM 2MV 94V-0
- Manifakti : UMC
- Peyi fabrikasyon : Taiwan
- Konstwi Ane/Semèn : 1996/39
- Kapasite Done : 256KB
- Pin count : 80pins
- Karakteristik : KÒT(Cache Sou Yon Baton), Pipeline pete kachèt, additional L2 Cache, SRAM
- Voltage : 3.3V
- Chip Konpozisyon : [UM61(L)3232AF-7 9641S MM4X52] ✕ 2 + [UM61(m)256s-15 9549D RB1121] ✕ 1
You forgot the most common colloquial term for these: COAST (Cache Sou Yon Baton) :P
I just know the term, KÒT(Cache Sou Yon Baton).
Thank you for your kind comment.